Multi-mode computing circuit

ABSTRACT

A single electrical circuit is capable of alternatively calculating an output voltage VO according to the general formula, VO VA (VC/VB)n or VO K 1n (VC/VB)T where VA, VB and VC are circuit input voltages and n, K, and T1 are determinable values of the circuit. A first relaxation oscillator may be selectively coupled to a second relaxation oscillator or to a chargeable capacitor supplied with constant current. The value of VO is repeatedly adjusted as a function of decaying response time. VO is computed when two response times are driven into equality.

United States Patent Brendle Jan. 8, 1974 [54] MULTI-MODE COMPUTING CIRCUIT 3,676,66! 7/1972 Sprowl 235/195 X .977 [75] Inventor: Thomas A. Brendle, Hamburg, NY. 3 7n 1/1973 Rlce 235/195 [73] Assignee: Audn Corporation, Hamburg, NY. rimary Examiner-Joseph F. Ruggiero A1: -S0 8: W b 22 Filed: Jan. 30, 1973 mmers e [21] App]. No.: 328,001 [57] ABSTRACT A single electrical circuit is capable of alternatively 52 US. (:1 235/195, 307/229, 307/294, calculating an Output voltage 0 according to the 2 320/1, 328/78 .eral formula, 51 1111.01 606g 7/16 V0 A B of 0 K a B) [58] Field of Search 235/195, 194, 196, Where 4 8 and 0 are circuit input voltages and n, 2 5 5; 3 7 293 9 22 23 K, and T, are determinable values of the circuit. A 14 4 no 7 first relaxation oscillator may be selectively coupled to a second relaxation oscillator or to a chargeable ca- [56] References Cited pacitor supplied with constant current. The value of UNITED STATES PATENTS V is repeatedly adjusted as a function of decaying re- 3 043 5 7/1962, Abb u t l 235,193 X sponse time. V is computed when two response times o e a i 3,383,501 5/1968 Patchell 235/195 are equalty 3,549,874 12/1970 Vachitis 235/195 x 32 Claims, 6 Drawing Figures 551, 1 l s'lT u l uouosnate I MLLTIVIBRATOR l2 54w VB 2| I M52; 53}

A L W sA i' i c E51 f 13 22 23 25 62 ReLAxmou OSCILLATOR g PATENTEUJAI 81974 3.784 803 SHEZEI 2 UP 4 MJmSPmOZOZ PATENTEDJAH 81974 3.784.803 sum w 4 Iii x? TlME o asvnoA s BQVIIOA MONOSTABLE MULTIVIBRATOR PULSE TIME MULTI-MODE COMPUTING CIRCUIT BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrical circuit capable of calculating an output voltage V as a function of variable input voltages, V,,, V and V according to the general formulae,

V0 VA( VC/VB)" 01' V0 K In where 1n represents a natural logarithm and n, K, and T, are determinable constants of the circuit.

2. Description of the Prior Art A digital computer is capable of calculating a plurality of mathematical modes, such as division, multiplication, and the like, only if programmed to perform the desired function. However, many of such digital computers involve complicated and expensive structure, rendering their use impractical for many potential users. Beyond the cost of the physical structure, the degree of technical sophistication needed to program and operate such computers further adds to their'total cost.

A non-electrical system may often be reproduced in its electrical equivalency by an analog computer. While many mechanical elements have simple and inexpensive electrical analogs, still others require costly electrical hardware. Additionally, the assembly and operation of the analogous electrical circuit requires the exercise of a high degree of technical skill.

Still other computers are hybrid combinations of digital and analog logic. While unique capabilities may often be obtained with such systems, the inherent high costs of structure, programming, and operation are still present.

SUMMARY OF THE INVENTION A single multi-mode computing circuit is capable of calculating an output voltage V as a function of variable input voltages V,,, V,, and V according to the general formulae,

0 VA c/ n 0 K a/ H where V, is greater than V,, and n, K, and T, are determinable constants of the circuit.

The circuit has enerigzing means for simultaneously charging a first relaxation oscillator with V and a second relaxation oscillator with V for a determinable finite time period. After the time period expires, the oscillators are simultaneously permitted to decay. The voltages and response times required for V to fall to V and for V to fall to V are'sensed and compared in first and second comparator means, respectively. Correction means are provided to adjust the value of V for urging the difference in the response times to decrease. Sequencing means are operated by the comparator means for causing V to be successively recalculated. When the response times are equal, the circuit calculates V V, (V V Alternatively, an element of the second relaxation oscillator may be replaced; and a capacitor may be supplied with constant circuit, selectively dischargeable to ground. While the first relaxation oscillator decays, the capacitor is permitted to charge. The correction means adjusts and calculates V The sequencing means causes V to be recalculated, thereby to compute V =K in (V c/ V when the response times are equal. The time required by the circuit to calculate V is adjustable regardless of the general formula selected.

One object of the present invention is to provide a single electrical circuit capable of calculating an output voltage V as a function of variable input voltages V,,, V,,, and V according to the general formulae, V V,, (V /V or V K In (VC/VB)TI where V is greater than V, and n, K and T, are determinable constants of the circuit.

Another object is to provide a computing circuit which calculates an output voltage V by driving the response times of two decaying relaxation oscillators into phase and frequency equality.

Another object is to provide a computing circuit capable of providing a variable analog output signal as a function of variable analog input signals through the use of intermediate digital logic.

Another object is to provide a computing circuit capable of varying the time required to obtain a desired calculation.

Another object is to provide a computing circuit wherein the output or calculated signal is sampled and employed as a feedback signal.

Another object is to provide a computing circuit wherein the calculation of V is mathematically exact.

Still another object is to provide a relatively simple and inexpensive computing circuit.

These and other objects and advantages will become apparent from the foregoing and ongoing specification, the drawings, and the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic representation of the circuit producing an output voltage V as a function of input voltages V,,, V,,, and V FIG. 2 is a schematic wiring diagram of the circuit depicted in FIG. 1 and capable of performing the functions,

0 A A c/ B)" of 0 K a/ H where n, K and T, are determinable constants of the circuit.

FIG. 3 is a graphical illustration of the operation of the circuit in calculating V V, (V /V as the input voltages are varied.

FIG. 4 is a graphical illustration of the operation of the circuit in calculating V,, K In (V -/V,,) 1 as the input voltages are varied.

FIG. 5 is an elevational view of a cylindrical pipe discussed in the hypothetical practical illustration.

FIG. 6 is a schematic view depicting the manner in which three circuits and a differential amplifier may be combined to solve the complicated equation of the hypothetical practical illustration.

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Eqn. 2) V K In V /V FI where K and T, are dc.-

terminable constants.

As used herein, the term mode" refers to a mathematical calculation or computation, such as multiplication; division; raising a number (or a ratio) to a power; extracting a root from a number (or a ratio); taking the natural logarithm of a number (or a ratio); or multiplying a natural logarithm by a constant to obtain, for example, a logarithm to a different base. Either of the alternative general formulae specified above are capable of performing more than one mode of operation.

In Equation 1: if V l and n l, V V V (simple multiplication); if V,, 1 and n l, V V /V (simple division); if n 1, V V,, (V /V (a multiplier times a ratio); if V, =1, V =1, and n 3, V V (cube);

if V, 1, V,, l, and n 1/3, V V (cube root);

THE CIRCUIT (FIG. 2)

A computing circuit capable of calculating V as a function of the variable input voltages according to the general formulae specified in Equations 1 and 2 is schematically illustrated in FIG. 2.

The three input terminals 11, 12 and 13 are shown receiving their respective voltages, V,,, V,;, and V The output voltage V is available at output terminal 15. The circuit broadly includes two identical voltage comparators A, and A an AND gate, a monostable multivibrator, a voltage source V, a constant current source 1' two RC relaxation oscillators, a buffer amplifier, and a capacitor C,, along with a plurality of electronic (ES) and manual (MS) switches and resistors,(R).

The identical voltage comparators A, and A, have a high input impedance and receive their input voltages at terminals 2 and 3 to produce an output signal at ter minal 6. If the voltage on terminal 3'is greater than at terminal 2, the comparator will produce a positive out, put signal at terminal 6; if the voltage at terminal 3 equals that at terminal 2, the comparator. will produce a null or zero signal at terminal 6; if the voltage at terminal 3 is less than that at terminal 2, the comparator will producea negative output signal.

The monostable multivibrator may be excited or triggered into its quasi-stable state to produce a positive pulse output for a finite period of time, r after expiration of which it reverts to its stable state having a negative output. Preferably, the multivibrator has an adjustable quasi-stable state to permit 1,, to be varied, thereby to alter the length of time of the triggered positive pulse. With the capability of adjusting the length of time t,, that the monostable multivibrator remains excited in its quasi-stable state, the time required for the circuit to calculate V may be varied. Thisfeature is of tremendous significance. For example, if the circuit is merely to perform a mathematical calculation, 2,, may

In the well known manner, the AND gate will produce a positive output only if its'input signals are both positive. If either'or both of its input signals are negative, the AND gatewill maintain a negative output.

The buffer amplifier has a high input impedance and a low output impedance and has a gain of approximately one, which need not be stable or linear.

Input voltage V, is applied to the computing circuit at input terminal 11 and is directed to terminal 3 of comparator A through manual switch MS,, and conductor 20. Input voltage V,, is applied at input terminal 12 and is directed, to terminal'3 of comparator A, through conductor 21, Input voltage V is applied at terminal 13 and is directed to terminal 2 of comparator A, through conductor 22, electronic switch ES,, and conductors 23, 24.

A first relaxation oscillator network is connected to terminal 2 of comparator A, between conductors 23 and 24 by a conductor 25.

The first relaxation oscillator has a variable resistor R, connected to conductor 25 by a conductor 26, and connected to ground wire 28 by conductor 29; and has a capacitor C, connected in parallel with R, by conductors 30, 31 connected to conductor 25 and to ground wire 28, respectively. The first relaxation oscillator means includes this first relaxation oscillator network.

The calculated voltage V is supplied to terminal 2 of comparator A from the buffer amplifier through conductors 33, 34 and 35, electronic switch E5 and conductors 36, 37 and 38.

The second relaxation oscillator network is connected to terminal 2 of comparator A between conductors 37 and 38 by a conductor 39, manual switch MS,, and conductor 40. The second oscillator has a resistor R connected to conductor 40 by conductors 41 and 42 and manual switch MS,,, and connected to,

ground wire 43; and has capacitor means such as a capacitor C connected in parallel with R by a conductor 44 connected to conductor 40 and by conductor 45 connected to ground wire 43. The'second relaxation oscillator means includes this second relaxation oscillator network. i I i 7 Manual switch MS, maybe moved to its phantom position to disconnect the second relaxation oscillator networkfrom terminal 2 of comparator A and to connect conductor 40 to a constant circuit source i Manual switch MS, may be selectively closed to provide a shunt around electronic switch ES, and is connected by conductor 46 between conductors 36 and 37, and by conductor 48 between conductors 35 and 34.

Manual switch MS,, may be moved to its phantom position to disconnect R from conductor 42 and to connect a branch in parallel with C including conductor 49, electronic switch E8 and conductor 50 connected to ground wire 43.

Manual switch MS, may be moved to its phantom position to disconnect input voltage V,, and to connect conductor 20 to conductor 41 through an intermediate conductor 51.

The output signal produced at terminal 6 of comparator A, is received as a first input signal to the AND gate through conductor 52. Similarly, the output signal produced at terminal 6 of comparator A is received as a second input signal to the AND gate through conductor 53. If the signals in conductors 52 and 53 are both positive, the AND gate will trigger the monostable multivibrator into its quasi-stable state through conductor 54. When so excited, the multivibrator produces a posithe pulse output for a predetermined period of time, 1,,

which is employed to close B8,, B8,, and ES, for a corresponding period of time, as shown schematically by dashed lines 55, 56, 58, 59 and 60. The sequencing means includes the AND gate.

A voltage source V is grounded through a series circuit including conductor 61, electronic switch E8 resistors R, and R electronic switch ES, and ground wire 62. Electronic switches ES, and ES, are operated by the comparator output signals in conductors 53 and 52, respectively, as shown schematically by dashed lines 63 and 64. Therefore, ES, will close when the output signal of comparator A, is positive, and open when it is negative. Similarly, ES, will close when the output signal of comparator A, is positive, and open when it is negative. The correction means thus comprises a voltage supply circuit including voltage source V, ES, and resistor R and a voltage drain circuit including R ES, and ground wire 62.

A capacitor C, is grounded by ground wire 65 and is connected between resistors R, and R, by series conductors 66 and 68. Conductor 32 is shown connected between conductors 66 and 68.

The energizing means includes the monostable multivibrator and electronic switches ES,, ES, and ES, The first electronic switch means comprises ES,; and second electronic switch means comprises ES,; and the third electronic switch means includes ES The first and second comparator means includes comparators A, and A,, respectively.

As used herein, the term relaxation oscillator means broadly includes other known and functionally equivalent RC and RL circuits wherein a voltage may be permitted to decay to a lower value in a reproducible manner.

Derivation of V, V, (V /V With the four manual switches M8,, MS,, MS, and

, MS, moved to the positions indicated by the solid 1 lines in FIG. 2, the circuit is prepared to calculate The three input voltages, V,, V, and V,-, are each applied to their respective input terminals, ll, 12 and 13. V, is either selected or scaled to a greater value than V,,. Similarly, the internal voltage source V is provided at a greater value than V,,. I

Assume that initially the circuit is arranged such that all electronic switches are open and the several capacitors are discharging to low values. V and V, will be applied to terminals 3 of comparators A, and A,, respec tively. Since ES, is open, V, will not be applied to terminal 2 of comparator A,. Since ES, is open, V, will not be applied to terminal 2 of comparator A,. Therefore, the voltage at terminals 3 will be greater than that at terminals 2 of both comparators A, and A,.

At this instant, the output signals of both comparators will simultaneously be positive. ES, and ES, will be closed, grounding voltage source V through series resistors R, and R, and charging capacitor C, to some value. Receiving two positive input signals, the AND gate triggers the monostable multivibrator into its quasi-stable state to close ES, and ES, and to apply V and V to comparators A, and A,, respectively. Since lf is greater than li tle output of comparator A, will 6 flip from positive to negative, opening E5 andadjus t ing the value of V If V, is greater than V,,, the output signal of comparator A, will simultaneously flip from positive to negative, opening BS When ES, and ES, are both open, the voltage across capacitor C, is fixed. Accordingly, the value of V, will be fixed.

ES, and ES, are closed when the multivibrator is trig- ;gered into its quasi-stable state. During this time t,,, capacitor C, is charged to V and capacitor C, is charged to V0- After time period t, expires, the multivibrator reverts to its stable state, opening 158,, ES,, and ES, Both ca- :pacitors of the relaxation oscillator networks begin to .decay which is sensed at terminals 2 of the respective comparators. During such decay, the current in the first oscillator is given by the formula, i, =1}, e- "1 1. Tlhifially, sv m i s id C RQKWQFLL When the first relaxation oscillator decays to the flip voltage V,,, the current will be i,,, ,=V,,/R,. Substituting for i, and and solving for At,, the time required for this decay:

VII/VG e A l l.

VC/VB e A l /RlCl i (VC/ BVH where At, response time of first relaxation oscillator to decay from V, to V,,.

Similarly, the decaying current in the second oscillator is given by the formula:

, ioe 4/12 0,

When ES, opens,

i2 R2CZ After the second oscillator decays from V, to V,, the flip voltage,

2 m flip x/ z Substituting and solving for At,:

VO/VA e A 1 1x 0 At, ln (V l V, )"f; where t, response time for second oscillator to decay from V0 to VA. A

If At, is less than At,, ES, will close before E8 draining C, and decreasing V, until V, V,,. Conversely, if :the second oscillator decays to flip A, before the first oscillator decays to flip A,, At, will be less than At,, closing ES, before ES, to charge C, and to increase V Thus, the value of V is adjusted and caused to be readjusted on every sequence to urge the response times to equal each other.

Finally, when the response times are equal such that At Atz,

0 VA c/ B) l l "2 2 If n R,C,/R,C,, the following derivation obtains:

0 VA a/ s) 'where n may be selectively varied by adjusting variable resistor R,.

Derivation of V K In (V /V With manual switches MS,, M5,, M8,, and MS, moved to the positions indicated by the phantom lines of 2, the circuit is rented tqsalsslatslio 5.15. 1

V /V where K and T, are determinable constants of the circuit. When so moved to their phantom positions, MS, connects C to a constant current source i MS provides a shunt around E8 M8,, disconnects V and connects C to terminal 3 of comparator A In this configuration, the constant current source i is continuously applied to capacitor C When E8 closes, the current source is grounded and C is permitted to discharge.

With the monostable multivibrator in its stable state, ES, and ES, are open. Voltage V,, is applied toterminal 3 of comparator A generating a positive A, comparator output signal to the AND gateand closing BS Since BS, is open, the current source begins to charge C, which is also sensed on terminal 3 of comparator A Capacitor C charges according to the formula,

Since, i i,,, a constant,

In some time interval At capacitor C, will have charged with a voltage E equal to V Substituting and solving for t,:

Again V is adjusted and readjusted such that the response time of the capacitor to the value of V is urged to equal the response time of the first relaxation oscillator during decay. Finally, the response times will be urged into equality, or,

At, ln (V /V "1 Atg VoCg/iK Substituting and solving for V V0 K/ Z t/ B) R1. C1

or, I

0 c/ B) l 1 where T, R,C, and K i /C all determinable constants of the circuit.

When performing this function, the relaxation oscillator means includes first relaxation oscillator.

Operation of V,, V,, (V /V Function (FlG. 3)

FIG. 3 graphically represents the operation of the circuit in computing the function, V,, V, (V /V The numbered pulses of the monostable multivibrator are vertically aligned with the corresponding peak voltages in C, above and C, below, respectively.

At the first and second mono pulses, the circuit is depicted calculating V,, 4 when V,, 2, V,, l, and V,- 2. The response times Al, and At, are shown to be equal, indicating that V,, 4 is the desired calculation.

Voltage V,, is then increased from 2.0 to'2.5 in the interval between pulse 2 and the completion of pulse 3. Capacitor C, is again charged with V and is permitted to decay to V Since V, 4 is still greater than the increased value of V,,, capacitor C is again charged with V 4, but decays to the lesser value, V, 2.5, faster than V decays to V,,. In this situation, At, is less than. -At,. Hence, ES, closes before ES increasing V to pulse 4. Voltage V still decays to voltage V in the same time, At,. However, adjusted voltage V,, now de cays from a higher value, tending to increase At,. The

"response between pulses 4 and 5 illustrates V at some intermediately adjusted value. Upon decay, Ar, is still ,less than A1,, again causing V to increase. Sequential pulse 5 represents a readjusted value of V When V has performed the desired calculation, At, will equal At as shown in the intervals between pulses 5 and 6 i and pulses 7 and 8.

If V is'decreased from 2.0 to L5 betweenpulses 7 and 8, capacitors C, will charge to the now lowered value of V 1.5. The change in V is not immediately known to V,,, which again charges to V, 5. After r expires, V will decay to V, before V,, will decay to V or, At, is less than At ES, will open before ES, to adjust V,, to some decreased value, represented at pulse 9. Voltage V will be sequentially readjusted until At, equals At as represented by the equal response times between pulses 10 and 11. When At, equals At V equals 3.75, the desired computation.

Now if V,, is decreased from 1.0 to 0.75 between pulses l1 and 12, capacitor C, will take longer to decay to the decreased value of V than'capacitor C will take to decay from the previous V to V or, At, will be greater than At Hence, ES, will close before E5 causing V to increase as shown at pulse 13. Again V is sequentially readjusted to urge At, to equal At,, A

which situation is illustrated between pulses 14 and 15, and pulses l5 and 16.

Voltages V and V,, are shown increased to 2.0 and 1.0, respectively, between pulses 16 and 17. At pulse 17, C, will charge to the higher value of V, and take longer to decay to the lower value of V,,, as shown between pulses l7 and 18. If V, is decreased to 2 between pulses 17 and 18, V will also take longer to decay. Electronic switch ES, will open first, increasing V, at pulse 18. Finally, At, will equal'At, and the desired computation will have been performed, as in pulses l9 and 20, and pulses 21 and 22.

By varying adjustable resistor R,, the exponent n can be varied according to the formula, n R,C,/R C In the response graphically depicted in the rightward portion of FIG. 3, R, has been adjusted such that, n 2 to perform a squaring function. The response times are initially shown to be equal between pulses 28 and 29 and pulses 29 and 30 so that V,, 2.25 when V,, 1, V,, l, and V l.5. If V is increased to 2.0 between pulses 30 and 31, V will charge to this higher value at pulse 31. When ES, and ES, are open, the response time of the first oscillator to decay from V to V,, will take longer than the corresponding decay of the second oscillator from the previous V to V Hence, At, will be greater than At causing ES, to open first and adjust the value of V,,, as represented in sequential pulse 32. The adjustment of V continues until At, equals At,, indicating performance of the desired computation, as indicated at pulses 33, 34 and 35. 3

Operation of V, K In (V /V l Function (FIG. 4)

FIG. 4 graphically represents the operation of the circuit in computing V., K in (V /V lf initially, V 4, V 8, K l, and T, l, the circuit is initially shown as calculating V, 1n (2) at pulses 1, 2 and 3.

When the monostable multivibrator closes ES, and ES, for time t,,, C, is charged with V and C, is permit- ;ted to discharge through conductors 44, 41, 42, 49, and 43. Hence, when C, is permitted to charge, C is some higher adjusted alge as illustratedg sequential fpermitted to discharge. After r expires ES, -and ES open, permitting capacitor C, to decay and permitting capacitor C to be charged with i Hence, C, is decaying when C is charging.

If V is decreased to 1.0 between pulse 4 and pulse 5, C, will take longer to decay to the lowered value of V If capacitor C charges to the value of V first, At will beless than At,, causing ES, to close first, increasing V Again the system urges At, to equal At as shown between pulses 6 and 7 and pulses 7 and 8. Thus, if V 8 decays to V l in A2,, C will charge to a higher value of V, ln (8) in the same time, indicating performance of the desired computation.

If V is increased to between pulses 7 and 8, C, will be charged with V during pulse 8. Hence, At, will be longer for capacitor C, to decay from 15 to 1; C will cause ES, to close first, increasing V At At, At V, In (15) will be calculated.

If V, is increased to 5 between pulses l0 and 11, the response time of C, in decay will be shortened, opening E8 before 88,, to decrease V As At is shortened, capacitor C charges to a lower value, finally when At, A1,, V In (5) is calculated.

PRACTICAL ILLUSTRATION For purposes of illustrating the utility of further combinations of the inventive circuit, assume that it is desired to calculate the heat conducted through some or all of the pipes in an oil refinery.

Referring to FIG. 5, a long hollow pipe 80 is depicted as having an inner radius r, and an outer radius r,,. Assume that a fluid heats the inner surface to T, while the outer surface is at temperature T The rate of heat conduction, q, is given by the general formula,

2'rr a constant K coefficient of thermal conductivity L length T,- temperature inside pipe T temperature outside pipe r outer radius r, inner radius Three circuits and a differential amplifier may be uniquely combined to calculate q, as a function of multiple variables, as best shown in FIG. 6.

In FIG. 6, circuit No.1 is prepared to calculate V V (V /V The input voltages are selected such that V,, K, a variable; V,, l/21r, a constant; and V L, a variable. Substituting the input voltages into the general equation produces an output voltage V 21rKL.

Circuit No.2 is prepared to calculate V (i /C In (V /V 1 where T, l, and MC, K= 1. Input voltages V and V are selected to represent the radii, r, and r respectively. Substituting the input voltages of V and V into the general equation produces an output signal V In (r,/r

A differential amplifier receives the voltages analog of two temperatures, T, and T produces an output signal equal to their difference, (T, T

Circuit No.3 is prepared to calculate V V (V /V with n=l. The output voltage V of the circuit No.1 is received as input voltage V to circuit No.3; the output voltage V of circuit No.2 is received as input voltage V and the output voltage of the differential amplifier, (T, T is received as input voltage V Substituting these input voltages into circuit No.3 produces an outputsignal, V 21'rKL (T, T,,),/[ ln (r,/r,,)], the desired computation. Thereafter, any of the variables K, L, T,, T,,, r,, and r may be varied.

The foregoing practical illustration is intended merely to demonstrate that two or more of the unique circuits herein disclosed may be combined to perform a more complicated computation. The practical illustration further demonstrates that the inventive circuit may be combined with a differential amplifier, as needed. Should an equation involve addition, a summing amplifier could be used.

The various electrical and electronic components discussed hereinabove are well known to the skilled in the art and therefore require no more specific description.

What is claimed is:

l. A multi-mode computing circuit capable of calculating an output voltage V as a function of three variable input voltages, V,,, V,,, and V according to the general formula, V V,,( V V,,)', where V is greater than V and n is a determinable value of the circuit, comprising:

first and second relaxation oscillator means;

energizing means for simultaneously charging said first oscillator means with V and said second oscillator means with V for a finite time period and for permitting decay of both of said oscillator means after said time period expires;

first comparator means for comparing the voltage in said first oscillator means with V and for sensing the response time of said first oscillator means during decay;

second comparator means for comparing the voltage in said second oscillator means with V and for sensing the response time of said second oscillator means during decay;

correction means controlled by the voltages compared at said first and second comparator means for adjusting the value of V and for urging the difference of said response times to decrease; and sequencing means operated by said first and second comparator means for successively activating said energizing means after V has been adjusted to cause V to be readjusted and to calculate V,, V, (V(:/ V,,)" when said response times are equal.

2. The circuit of claim I wherein said energizing meanspermits simultaneous decay of both of said oscillator means.

3. The circuit of claim 1 wherein said energizing means is adjustable to permit said finite time period to be varied.

4. The circuit of claim 2 wherein said first oscillator means includes a RC circuit having a resistor R,

arranged in parallel with a capacitor C,.

5. The circuit of claim 4 wherein said second oscillator means is a RC circuit having a resistor R arranged in parallel with a capacitor C 6. The circuit of claim 5 wherein n R,C,/R C

7. The circuit of claim 6 wherein R, is an adjustable resistor for permitting n to be varied.

8. The circuit of claim 1 wherein said first comparator means is a voltage comparator capable of generating a positive output signal when the voltage in said first oscillator means is greater than V a negative signal when such voltage is less than V and a null signal when such voltage is equal to V 9. The circuit of claim 1 wherein said second oscilla- V tor means is a voltage comparator capable of generating a positive output signal when the voltage in said secnal when such voltage is less than V,, and'a null signal when suchevoltage is equal to, V I

10. The circuit of claim 3 wherein saidenergizing means includes first electronic switch means between V and said first oscillator means, second electronic switch means between V and said second oscillator means, and a monostable multivibrator operatively-associated with said first and second electronic switch means to close said switch means when said multivibrator is excited into its quasi-stable state and to open said switches when said multivibrator reverts to its stable state.

11. The circuit of claim wherein said monostable multivibrator is adjustable to vary said finite time period.

12. The circuit of claim 1 wherein said sequencing means includes an AND gate.

13. The circuit of claim 1 wherein said correction means includes a voltage supply circuit operated by said second comparator means to increase V when said response time of said second oscillator means is less than said response time of said first oscillator means.

14. The circuit of claim 13 wherein said correction means further includes a voltage drain circuit operated by said first comparator means todecrease V when said response time of said first oscillator meansis less than said response time of said second oscillator means.

15. The circuit of claim 14 wherein said correction means further includes capacitor arranged in parallel with said voltage drain circuit.

16. The circuit of claim 15 further comprising a buffer amplifier between said correction means and said second comparator means.

17. A multi-mode computing circuit capable of calculating an output voltage V as a function of two variable input voltages, V and V according to the general formula, V K ln (VC/V")T1 where V is greater than V and where C and T are determinable values of the circuit comprising:

relaxation oscillator means;

a source of constant current;

capacitor means supplied with said constant current;

energizing means for simultaneously charging said oscillator means with V and for draining said capacitor means for a finite time period and for permitting said oscillator means to decay and said capacitor means to charge after said time period expires;

first comparator means for comparing the voltage in said oscillator means with V and for sensing the response time of said oscillator means during decay;

second comparator means for comparing the voltage in said capacitor means with V and for sensing the response time of such capacitor means during charging;

correction means controlled by the relative voltages compared at said first and second comparator means to adjust V for urging the difference between said oscillator response time and said charging capacitor means response time to decrease; and sequencing means for successively activating said energizing means after V has been adjusted to cause V to be readjusted and to calculate V K ln( V V 1 when said response times are equaLi 18. The circuit of claim 17 wherein said energizin'g means simultaneously permits said capacitor means to charge and said oscillator means begins to decay.

19. The circuit of claim 18 wherein said oscillator means includes an RC circuit having a resistor R arranged in parallel with a capacitor C 20. The circuit of claim 19 wherein T R C,.

21. The circuit of claim, 20 wherein R is an adjustable resistor for permitting T, to be varied.

22. The circuit of claim 17 wherein said energizing means is adjustable to permit said finite time period to be varied.

23. The circuit of claim 22 wherein said first comparator means is a voltage comparator capable of generating a positive output signal when the voltage in said oscillator'means is'greater than V,,, a negative signal when such voltage is less than V and a null signal when such voltage is equal to V 24. The circuit of claim 18 wherein said second comparator means is a voltage comparator capable of generating a positive output signal when the voltage in said capacitor means is greater than V a negative signal when such voltage is less than V and a null signal when such voltage: is equal to V 25. The circuit of claim. 22 wherein said energizing means includes first electronic switch'means between V and said oscillator means, third electronic switch means arranged in parallel with said capacitor means, and a monostable multivibrator operatively associated with said first and third electronic switch means to close said switch means when said multivibrator is excited into its quasi-stable state and to open said switch means when said multivibrator reverts to its stable state.

26. The circuit of claim 25 wherein said monostable multivibrator is adjustable to vary said finite time period.

27. The circuit of claim 18 wherein said sequencing means includes an AND gate.

28. The circuit of claim 18 wherein said correction means includes a voltage supply circuit operated by said second comparator means to increase V when said response time of said capacitor means during charging is less than said response time of said oscillator means during decay.

29. The circuit of claim 28 wherein said correction means further includes a voltage drain circuit operated by said first comparator means to decrease V when said response time of said oscillator means during decay is less than said response time of said capacitor means during charging.

30. The circuit of claim 29 wherein said correction means further includes a capacitor arranged in parallel with said voltage drain circuit.

31. The circuit of claim 30 further comprising a buffer amplifier between said correction means and said second comparator means.

32. The circuit of claim 17 wherein said capacitor means is a capacitor.

" UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION- Patent No. 3,784,803 Dated January 8, 1974 Inventofls) C "Thomas A. Brendle It is certified that error appears in the'above-identified patent: and that said Letters Patentare hereby corrected as shown below:

E itle page: the identified Attorney should be Sommer & Weber- ABSTRACT, line 4:, the second equation should be- -V =Kln,(V /V Col. 1, line 41: "enerig'zing" should be --energizing--; Col. 2, line 36.: the first equation should be --V =V (V /V Col. 6, line 18% a fi er "Substituting," the equation hould be --i= v /R e Col. 7, line 22: should be--At Col. 8, line 12,: "capacitors" should e oapacitor-; 7 Col. 9, line 21: "value, finally" should be value. Finally---;

, li 1m "V should 'be -V l-V;

Col. 10, line 2; the equation should be --V 3=2lTKL (Tv ---T )/[ln(r /r line 14: "the" should be -those-; Claim 15, line 2: "includes capacitor"-fshould be v-incl udes.a

capacitor-; t Claim 17, line 5: "C" should be --K-; 4 Claim 18, line 3: "begins" should be deleted.

Signed and sealed this 23rd day; "of April l97h.

(SEAL) Attest:

EDWARD I-I.FLETCHER,JR. C l-IARSHALL DAL-{'11 Attesting; Officer Commissioner of Patents Col. 7, line 22: "t should be --Atgmg?" um'rmn s'rA'rEs PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,784,803 Dated January 8, 1974 Inventofls) "Thomas A. Brendle It is certified that error appears in the above-identified patent and that said Letters Patentare hereby corrected as shown below:

Title page: the identified Attorney should be -Sommer & Weber-5;

ABSTRACT, line 4:]the second equation should be- -V =Kln.(V /V Col. 1, line 41: "enerig'zing" should be -energizing--; Col. 2,-' line 36: the first equation should be --V =V (V /V Col. 6, line 18': after "Substituting," the equation hould be Col. 8, line 12': "capacitors" should e -capac'itor-; Col. 9, line 21: "value, finally" should be value." Finally--;

, li 1 7: "V should be --V l- Col. 10, line 2 the equation should be --V03=2|TKL (T, --T )/[ln (r /r line- 14: "the" should be ---those-; Claim 15, line 2: "includes capacitor'P'should be -includes,a

capacitor-; Claim 17, line 5: "C" should be --K;. Claim 18, line. 3: "begins" should be deleted.

Signed and sealed this 23rd day of April 197R.

(SEAL) Atte st:

229mm) I-I.FLETc2-LE- ,JR. I v c. MARSHALL Din-{11 Attesting Officer I V Commissions of Patents 

1. A multi-mode computing circuit capable of calculating an output voltage VO as a function of three variable input voltages, VA, VB, and VC, according to the general formula, VO VA(VC/VB)n, where VC is greater than VB and n is a determinable value of the circuit, comprising: first aNd second relaxation oscillator means; energizing means for simultaneously charging said first oscillator means with VC and said second oscillator means with VO for a finite time period and for permitting decay of both of said oscillator means after said time period expires; first comparator means for comparing the voltage in said first oscillator means with VB and for sensing the response time of said first oscillator means during decay; second comparator means for comparing the voltage in said second oscillator means with VA and for sensing the response time of said second oscillator means during decay; correction means controlled by the voltages compared at said first and second comparator means for adjusting the value of VO and for urging the difference of said response times to decrease; and sequencing means operated by said first and second comparator means for successively activating said energizing means after VO has been adjusted to cause VO to be readjusted and to calculate VO VA (VC/VB)n when said response times are equal.
 2. The circuit of claim 1 wherein said energizing means permits simultaneous decay of both of said oscillator means.
 3. The circuit of claim 1 wherein said energizing means is adjustable to permit said finite time period to be varied.
 4. The circuit of claim 2 wherein said first oscillator means includes a RC circuit having a resistor R1 arranged in parallel with a capacitor C1.
 5. The circuit of claim 4 wherein said second oscillator means is a RC circuit having a resistor R2 arranged in parallel with a capacitor C2.
 6. The circuit of claim 5 wherein n R1C1/R2C2.
 7. The circuit of claim 6 wherein R1 is an adjustable resistor for permitting n to be varied.
 8. The circuit of claim 1 wherein said first comparator means is a voltage comparator capable of generating a positive output signal when the voltage in said first oscillator means is greater than VB, a negative signal when such voltage is less than VB, and a null signal when such voltage is equal to VB.
 9. The circuit of claim 1 wherein said second oscillator means is a voltage comparator capable of generating a positive output signal when the voltage in said second oscillator means is greater than VA, a negative signal when such voltage is less than VA, and a null signal when such voltage is equal to VA.
 10. The circuit of claim 3 wherein said energizing means includes first electronic switch means between VC and said first oscillator means, second electronic switch means between VO and said second oscillator means, and a monostable multivibrator operatively associated with said first and second electronic switch means to close said switch means when said multivibrator is excited into its quasi-stable state and to open said switches when said multivibrator reverts to its stable state.
 11. The circuit of claim 10 wherein said monostable multivibrator is adjustable to vary said finite time period.
 12. The circuit of claim 1 wherein said sequencing means includes an AND gate.
 13. The circuit of claim 1 wherein said correction means includes a voltage supply circuit operated by said second comparator means to increase VO when said response time of said second oscillator means is less than said response time of said first oscillator means.
 14. The circuit of claim 13 wherein said correction means further includes a voltage drain circuit operated by said first comparator means to decrease VO when said response time of said first oscillator means is less than said response time of said second oscillator means.
 15. The circuit of claim 14 wherein said correction means further includes capacitor arranged in parallel with said voltage drain circuit.
 16. The circuit of claim 15 further comprising a buffer amplifier between said correction means and said second comparator means.
 17. A multi-mode computing circuit capable of calculating an output voltage VO as a function of two variable input voltages, VB and VC, according to the general formula, VO K 1n (VC/VB)T , where VC is greater than VB and where C and T1 are determinable values of the circuit comprising: relaxation oscillator means; a source of constant current; capacitor means supplied with said constant current; energizing means for simultaneously charging said oscillator means with VC and for draining said capacitor means for a finite time period and for permitting said oscillator means to decay and said capacitor means to charge after said time period expires; first comparator means for comparing the voltage in said oscillator means with VB and for sensing the response time of said oscillator means during decay; second comparator means for comparing the voltage in said capacitor means with VO and for sensing the response time of such capacitor means during charging; correction means controlled by the relative voltages compared at said first and second comparator means to adjust VO for urging the difference between said oscillator response time and said charging capacitor means response time to decrease; and sequencing means for successively activating said energizing means after VO has been adjusted to cause VO to be readjusted and to calculate VO K 1n(VC/VB)T when said response times are equal.
 18. The circuit of claim 17 wherein said energizing means simultaneously permits said capacitor means to charge and said oscillator means begins to decay.
 19. The circuit of claim 18 wherein said oscillator means includes an RC circuit having a resistor R1 arranged in parallel with a capacitor C1.
 20. The circuit of claim 19 wherein T1 R1C1.
 21. The circuit of claim 20 wherein R1 is an adjustable resistor for permitting T1 to be varied.
 22. The circuit of claim 17 wherein said energizing means is adjustable to permit said finite time period to be varied.
 23. The circuit of claim 22 wherein said first comparator means is a voltage comparator capable of generating a positive output signal when the voltage in said oscillator means is greater than VB, a negative signal when such voltage is less than VB, and a null signal when such voltage is equal to VB.
 24. The circuit of claim 18 wherein said second comparator means is a voltage comparator capable of generating a positive output signal when the voltage in said capacitor means is greater than V0, a negative signal when such voltage is less than VO, and a null signal when such voltage is equal to VO.
 25. The circuit of claim 22 wherein said energizing means includes first electronic switch means between VC and said oscillator means, third electronic switch means arranged in parallel with said capacitor means, and a monostable multivibrator operatively associated with said first and third electronic switch means to close said switch means when said multivibrator is excited into its quasi-stable state and to open said switch means when said multivibrator reverts to its stable state.
 26. The circuit of claim 25 wherein said monostable multivibrator is adjustable to vary said finite time period.
 27. The circuit of claim 18 wherein said sequencing means includes an AND gate.
 28. The circuit of claim 18 wherein said correction means includes a voltage supply circuit operated by said second comparator means to increase VO when said response time of said capacitor means during charging is less than said response time of said oscillator means during decay.
 29. The circuit of claim 28 wherein said correction means further includes a voltage drain circuit operated by said first comparator means to decrease VO when said response time of said oscillator means during decay is less than said response time of said capacitor means during charging.
 30. The circuit of claim 29 wherein said correction means further includes a capacitor arranged in parallel with said voltage drain circuit.
 31. The circuit of claim 30 further comprising a buffer amplifier between said correction means and said second comparator means.
 32. The circuit of claim 17 wherein said capacitor means is a capacitor. 